PSOC5 VDDIO Power Domain Issues

In theory, you can use the VDDIO power pins to run the I/O ports at different voltage levels. This is true, except when it is not true.

You *must* run the VDDIO1 (supplies power for the P1 port, pin 17 on QFN package) power pin at around 3.3-5.0v at all times. If you don’t, you cannot program the PSOC 5, either from the USB port, or from the SWD/SWCLK lines. (I have not tested at 1.76v, it *might* work. I suspect it will not.) This means you cannot power the PSOC5 VDDIO1 after the core has powered up and become operational. It must be powered as part of the default board power system.

In the past, I have used the internal op-amps to power some of the VDDIO power lines to allow a 5V general voltage and a 3.3v voltage for certain I/O pins. That works, with some common sense conditions. (For example, don’t source a voltage into the port until the PSOC is powered up.) If you configure the PSOC immediately using DMA, and Power on the OpAmp first statement in main(), there is only a few microseconds where the pins are unpowered. This usually works without problems.

Interestingly enough, the Opamp / VDAC combination keeps the voltage within 0.1 volts all the way up to the maximum temperature rating for the PSOC5. Usually within 0.01 volts.

The PSOC5 is still not matched by any part out there, either from Infineon, or from competitors. Infineon is playing “ME2” in the processor space, deprecating the configuration system. It has problems that have to be worked around, but they are very few, given the amazing configurability of the part.

Final Note

I have found some new issues with the EEPROM on the PSOC5 at maximum specified operational temperatures. I suspect die shrinkage has weakened the EEPROM system, and it is now prone to some failures that were not seen in the past. We have been moving to external permanent storage components due to this problem.

Enjoy!