PSOC5: Pulse Detection and PGA (Programmable Gain Amplifier)
Posted On August 3, 2023
Going back 10 years to just before I discovered the PSOC5, picking pulses off of a line would require OpAmps, Voltage References, Multiple Power Supplies, bypass capacitors, resistors, and a lot of board space. This time it is different, even though I use the same parts. The difference is that I use a single PSOC5, and those parts are on the inside. And, with the ARM processor in charge, it can quickly adapt to the external world.
I will show the schematics, then explain the use. Interestingly enough, using a processor to tweak voltages in the circuit allows for a generic approach that can easily be tweaked for your situation.
The first schematic is the interface to the outside world. The second is the interface to the computer hardware. But first, some explanation of the problem.
The Truth About Pulses
Pulses on a line rise above the current line’s DC level (positive going pulses), or drop below the current line’s DC level (negative going pulses). You can set a reference that is short of the positive excursion of the positive going pulses, and just higher than the negative going pulse excursion, referenced to the current line’s DC voltage (the 0 point relative to the pulses), and detect when the pulses occur.
So, if too many pulses are positive, the average DC voltage level of the line increases. If too many are negative going pulses, the average DC voltage level of the line decreases. This is always a problem, and is usually solved by balancing the pulse stream (equal number of positive and negative pulses), or by using resistors to force the line to be at a constant DC voltage, or by filtering, or all of the above.
Resistors of correct size will bring the voltage back down to “normal” after a short period of time. The resistors are chosen to do this more quickly than the next pulse will come in. The disadvantage of this is the pulse heights are affected. The advantage of this is the average DC balance of the pulse stream does not have to be as good, and overall noise affecting the signal is also reduced.
Schematic Part Uno
In the schematic above, an external resistor on P3 connects to P3 and forces the line input to be at a certain voltage at P3. The signal into the PSOC is capacitively coupled so no DC signal from the line is introduced.
The PGA (Programmable Gain Amplifier) inside the PSOC5 has very little offset, and using an OPAMP to drive the analog voltage out provides a steady reference for the gain amplifier. The pulse signal is then amplified, without changing DC level and sent to the pga_out’s off-page connection. (DC level really is changed, but very, very little, and does not really affect what we are doing.) In addition, P0 brings the output of the PGA to a pin so an oscilloscope can monitor both DC and AC levels.
In my case, a PGA multiplier of either 2 or 4 worked well. I was able to monitor the signals and change the gain to automatically adjust for a short line versus a long line. So, the receiver was “hands free.” It just works!
Pulse Detection Hardware
The second part of the pulse detection is two comparators. These comparator are clocked by the PSOC5 clock fabric so the compared signal is synchronized with the internal digital fabric within the PSOC5 for future processing by the on board computer hardware. This becomes important quite often.
When the input signal’s pulse goes above the VDAC_TelemetryRxRefPos voltage level, the Comparator toggles and a digital signal is fed to other schematic sheets and eventually processed.
The same thing happens on the TelemetryRXRefNeg DAC output side. Contrary to what you might thin, both pulses were positive going, event though the RefNeg voltage DAC had a lower voltage out than the RefPos Voltage DAC. The Polarity on the Comp_Neg_Pulse output was chosen as Inverting in order to get this effect. (This option shows up as the circle on the output inside the Inverter block on the schematic.)
Schematic Part Dos
In the schematic below, I saw the Positive Pulses on the Positive_Pulses_In line, and Negative pulses on the other line. Success! Pulse based Telemetry was decoded over 20,000 feet of line.
In my implementation, there is about 200 millivolts difference between the two comparator references. Their outputs are offset 100mv above and below the previous schematic’s VDAC_TelemetryVRef during operation. (One thing to watch for: If the difference between the two comparator references and the line VREF is too small, the pulse detection tends to be extremely noisy or fail altogether. You can always send the voltages from the DACS out debug pins and check values with an oscilloscope or voltmeter.)
Over a long enough line, with capacitive coupled line drivers, pulses may undershoot or overshoot. Be careful when setting your references not to catch these un-wanted signals.
If you are receiving telemetry, and you cannot use reference voltages to get out of this problem, you can blank out the second edge of the pulse before it goes into your telemetry decoder logic. How I did that gets too close to magic. I have to leave it as an exercise for the reader. Can’t give away all my secrets!